1. Field of the Invention
The present invention generally relates to the field of photolithography, and, more particularly, to a writing methodology to reduce write time, and a system for performing same.
2. Description of the Related Art
Manufacturing modern integrated circuit devices requires the performance of many complex processes, such as deposition processes, etching processes, ion implant processes and photolithography processes. In general, photolithography involves the formation of a patterned layer of photoresist above a previously formed process layer. Ultimately, the underlying process layer will be subjected to one or more etching processes while using the patterned layer of photoresist as a mask. This will result in the selective removal of the portions of the process layer that are not protected by the photoresist masking layer. That is, a plurality of features, e.g., gate electrode structures, metal contacts, etc., will be formed in the underlying process layer. The patterned layer of photoresist is then removed and additional process operations are performed, e.g., additional layers of material are formed and selectively etched, until such time as the integrated circuit device is completed.
Photolithography is one of the most important, expensive and time-consuming processes performed in a modern integrated circuit manufacturing facility. In the photolithography process, a layer of photoresist material (positive or negative) is deposited on a process layer that has been formed above a semiconducting substrate, i.e., a wafer. There-after, the layer of photoresist is selectively exposed to a light source. More particularly, during the exposure process, radiant energy, such as ultraviolet light or deep ultraviolet light, is directed through a reticle to selectively expose the layer of photoresist. In this manner, the pattern in the reticle is transferred to the layer of photoresist. The layer of photoresist is then developed to remove the exposed portions of the layer of photoresist (for a positive resist material) to thereby define a patterned photoresist mask that is used in the subsequent etching of the underlying process layer. For negative photoresist materials, the unexposed portions of the layer of photoresist are removed during the development process. Additionally, the layer of photoresist is exposed to the light source on a flash-by-flash basis in a stepper exposure tool. The number of production die in each flash pattern may vary, e.g., a 2xc3x972 pattern (4 die), a 2xc3x974 pattern (8 die), etc. This step-by-step exposure process is continued until all of the areas of the production die on the wafer are exposed.
The manufacture and patterning of a reticle is a very time-consuming and expensive process. A reticle for use in manufacturing a modern integrated circuit product may cost between $25,000-$75,000, depending upon the type of reticle and the complexity of the reticle pattern. A reticle typically includes a transparent substrate comprised of, for example, quartz or glass. A very thin, opaque film is formed above the transparent substrate. The opaque film may be comprised of a variety of materials, such as chromium. To form the pattern in the reticle, a layer of photoresist material, e.g., a positive photoresist material, is formed above the opaque film, and an electron beam is used to expose selected portions of the layer of photoresist. Thereafter, the exposed portions of the layer of positive photoresist are removed, thereby exposing portions of the underlying opaque film, e.g., chromium. An etching process is then performed using the patterned layer of photoresist as a mask to remove the exposed portions of the opaque film, resulting in the desired pattern in the opaque film. The patterned layer of photoresist is then removed, and the reticle is ready for use in the photolithography process as described above.
Reticles are typically manufactured using high energy, approximately 50 keV, tools that employ a variable shaped beam, e.g., an electron beam tool, such as the Model No. EBM 3000 manufactured by Toshiba Machine. FIG. 1 is an enlarged plan view of a layout of a portion of a reticle 10. A pattern comprised of a plurality of illustrative features 12 that are to be formed in the opaque layer of the reticle 10 are shown in the layout. Typically, a semiconductor manufacturer will provide the desired pattern for the reticle 10 to a vendor that manufactures reticles in a binary digital format (Mebes). In turn, to develop a write pattern for an illustrative e-beam tool, the reticle manufacturer then fragments or divides the digital data representative of the overall desired reticle pattern into a plurality of non-overlapping, geometric shapes, e.g., rectangles, that correspond to the overall desired reticle pattern.
FIG. 2 is an illustrative example of one possible writing pattern for the reticle pattern shown in FIG. 1. As indicated therein, each feature 12 is fractured or sub-divided into four segments numbered 1-4 with no overlap between the rectangular segments. The specific process by which the reticle pattern data is fragmented may vary depending upon the reticle writing equipment employed and the reticle supplier. In some cases, the manner in which the fragmentation of the reticle pattern data is accomplished is proprietary to each particular reticle vendor. Once the reticle pattern data is fragmented, it is provided to the electron beam tool to write or expose the desired portions of the layer of photoresist that correspond to the fragmented segments 1-4 for each feature 12.
Depending upon the complexity of the desired reticle pattern, and the fragmenting process, the above-described technique can lead to very long reticle write times, e.g., greater than 12 hours for some complex reticle designs. Such a long lead time can be very problematic in the fast-paced environment of semiconductor manufacturing. For example, the designs of integrated circuit products and the processes used to make such products are under constant review in an effort to improve product performance, reduce manufacturing cost and increase the overall production yield of the manufacturing process. As a result, new reticles are frequently requested in attempts to upgrade or improve product design and/or manufacturing yields. However, given the relatively long writing times employed with existing techniques, quick turnaround of new reticle designs is very difficult. As a result, implementing product changes takes longer than would otherwise be desired. Moreover, existing techniques for producing reticles are very expensive due, in part, to the duration of the writing time for the reticle pattern.
Additionally, as device dimensions continue to decrease, the existing deep ultraviolet photolithography equipment may not be able to reliably pattern a layer of photoresist to the desired dimensions. As a result, the creation of faster and more powerful integrated circuit devices may be constrained due to the limits of deep ultraviolet photolithography tools and techniques.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to various writing methodologies to reduce write time, and a system for performing same. The present invention may be employed in the context of exposing a layer of photoresist during the course of manufacturing a reticle and/or exposing a layer of photoresist during the course of forming various features on production integrated circuit devices. In one illustrative embodiment, the method comprises exposing a layer of photoresist in accordance with a first writing pattern in a first area of the layer of photoresist and exposing the layer of photoresist in accordance with a second writing pattern in a second area of the layer of photoresist, wherein the first and second areas of the layer of photoresist overlap one another in at least one region. In other embodiments, the method further comprises creating the first and second writing patterns by separating digital data corresponding to a desired pattern for a reticle into at least two separate groups of data, a first of the data groups being used to define the first writing pattern and a second of the data groups being used to define the second writing pattern.
In another illustrative embodiment, the method comprises creating a collection of digital data corresponding to a desired pattern for a reticle and separating the collection of digital data into at least two separate groups of data, a first of the data groups being used to define a first writing pattern for the reticle, a second of the data groups being used to define a second writing pattern for the reticle, wherein the first and second writing patterns overlap one another in at least one region. In even further embodiments, the method further comprises separating the collection of digital data into at least three separate groups of data, a third of the data groups being used to define a third writing pattern for the reticle, wherein the third reticle writing pattern overlaps at least one of the first and second writing patterns in at least one region.
In a further illustrative embodiment, the method comprises forming a layer of photoresist above at least one of a semiconducting substrate and a process layer, exposing the layer of photoresist in accordance with a first writing pattern in a first area of the layer of photoresist, exposing the layer of photoresist in accordance with a second writing pattern in a second area of the layer of photoresist, wherein the first and second areas of the layer of photoresist overlap one another in at least one area, and removing exposed portions of the layer of photoresist in the first and second areas.
In another illustrative embodiment, the method comprises forming a layer of photoresist above at least one of a semiconducting substrate and a process layer, creating a collection of digital data corresponding to a desired pattern for the layer of photoresist, and separating the collection of digital data into at least two separate groups of data, a first of said data groups being used to define a first writing pattern for the layer of photoresist, a second of the data groups being used to define a second writing pattern for the layer of photoresist, wherein the first and second writing patterns overlap one another in at least one region.
In yet another illustrative embodiment, there is provided an exposure system that comprises an electron beam source and a controller that is adapted to direct electrons emitted by the electron beam source so as to expose a layer of photoresist in accordance with a first writing pattern in a first area of a layer of photoresist and expose the layer of photoresist in accordance with a second writing pattern in a second area of the layer of photoresist, the first and second areas of the layer of photoresist overlapping one another in at least one region.